Design of low power sequential circuit using clocked pair shared flip flop

@article{Nishanth2013DesignOL,
  title={Design of low power sequential circuit using clocked pair shared flip flop},
  author={N Nishanth and B. N. Sathyabhama},
  journal={2013 IEEE International Conference ON Emerging Trends in Computing, Communication and Nanotechnology (ICECCN)},
  year={2013},
  pages={759-763}
}
The clock system consisting of clock distribution networks and sequential elements is most power consuming VLSI components. Reductions of flip flop, power consumption have a deep impact on the total power consumption. Since power consumption is a major bottleneck of system performance, the clock load should be reduced to reduce the power consumption. The clock distribution network distributes the clock signal from a common point to all the elements that need it. Since this function is vital to… CONTINUE READING

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