Design of low-power quaternary flip-flop based on dynamic source-coupled logic

@article{Haixia2011DesignOL,
  title={Design of low-power quaternary flip-flop based on dynamic source-coupled logic},
  author={Wu Haixia and Zhong Shunan and Sun Zhentao and Qu Xiaonan and Chen Yueyang},
  journal={2011 International Conference on Electronics, Communications and Control (ICECC)},
  year={2011},
  pages={826-828}
}
A novel quaternary D-flip-flop is proposed by using dynamic source-coupled logic (SCL) for high performance processing element in VLSI system. Its key components, the threshold detectors, are based on differential-pair circuit (DPC). The combination of multiple-valued source-coupled logic and differential-pair circuit makes it low power and more compact. The performance is evaluated by HSPICE simulation with 0.18μm CMOS technology. The power dissipation, transistor numbers and delay are reduced… CONTINUE READING

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