Design of low power and high speed comparator with sub-32-nm Double Gate-MOSFET

@article{Bhumireddy2013DesignOL,
  title={Design of low power and high speed comparator with sub-32-nm Double Gate-MOSFET},
  author={V. R. Bhumireddy and Khaja Ahmad Shaik and Amara Amara and Supratim Sen and Chetan D. Parikh and Dipankar Nagchoudhuri and Adrian Ioinovici},
  journal={2013 IEEE International Conference on Circuits and Systems (ICCAS)},
  year={2013},
  pages={1-4}
}
A novel latch-based comparator is proposed for Successive Approximation (SA) Analog to Digital Convertor(ADC) with sub-32nm Double Gate MOSFETs(DG-MOSFET). The regeneration time of the latch is improved by using an extra positive feedback which uses the threshold voltage modulation property of DG-MOSFET. Simulation of the proposed comparator with CEA-LETI's DG-MOSFETmodels resulted in a delay of 25ps. The average power dissipation over one clock period is ≤ 1μW up to the clock frequency of… CONTINUE READING

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