Design of high speed MOS multiplier and divider using redundant binary representation

  title={Design of high speed MOS multiplier and divider using redundant binary representation},
  author={Shigeo Kuninobu and Tamotsu Nishiyama and Hisakazu Edamatsu and Takashi Taniguchi and Naofumi Takagi},
  journal={1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)},
A high speed multiplier and divider for MOS LSI based on a new algorithm is presented. When we implement the multiplier and the divider in LSI, the features such as high speed operation, small number of transistors and easy layout are the most important factors. A computational algorithm using a redundant binary representation has several excellent features such as high speed addition operations. We improved the algorithm and the method of implementation, and designed an advanced multiplier and… CONTINUE READING
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A 45ns 16x16 CMOS Multiplier,

  • Y. Kaji
  • IEEE International Solid-State Circuits…
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A VLSI-Oriented High-Speed Multiplier U ng A Redundant Binary Addition Tree,

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  • 1982

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