Design of high-performance power-aware asynchronous pipelined circuits in MOS current-mode logic

@article{Kwan2005DesignOH,
  title={Design of high-performance power-aware asynchronous pipelined circuits in MOS current-mode logic},
  author={Tin Wai Kwan and Maitham Shams},
  journal={11th IEEE International Symposium on Asynchronous Circuits and Systems},
  year={2005},
  pages={23-32}
}
This paper introduces the implementation of multi-GHz power-aware asynchronous pipelined circuits in MOS current-mode logic (MCML). The C-element and double-edge-triggered flip-flop are implemented in MCML and used in the so-called micropipeline circuits. An input data detector is proposed to put the inactive combinational logic into sleep mode. The effects of different layout techniques on the performance and power dissipation of an MCML FIFO are also investigated. Based on post-layout… CONTINUE READING

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Key Quantitative Results

  • The asynchronous MCML pipelined four-bit carry-look ahead adder with power-saving mechanism reduces the power dissipation by 32% compared to the one without the power-saving mechanism.

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