Corpus ID: 7722418

Design of an AES Device as Device Under Test in a DPA Attack

@article{Putra2018DesignOA,
  title={Design of an AES Device as Device Under Test in a DPA Attack},
  author={Septafiansyah Dwi Putra and Ma'muri and Sarwono Sutikno and Yusuf Kurniawan and Adang Suwandi Ahmad},
  journal={Int. J. Netw. Secur.},
  year={2018},
  volume={20},
  pages={256-265}
}
This paper presents a design for the implementation of the AES encryption algorithm in the hardware system. The proposed device is intended to be a device under test in a differential power analysis (DPA) attack. This device uses AES encryption with 128bit key length and electronic codebook (ECB) mode. The platform used in this device is FPGACyclone IV EP4CE115F29C7. AESAVS is used to test the functionality of the device. This study proposes a design for an AES-128 encryption device synthesized… Expand
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