Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips

@article{Chen1993DesignOA,
  title={Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips},
  author={Tom Chen and Glen Sunada},
  journal={IEEE Trans. VLSI Syst.},
  year={1993},
  volume={1},
  pages={88-97}
}
Absfract-This paper presents a memory architecture with the capability of self-testing and self-repairing. The contributions of this memory architecture are twofold. Firstly, it incorporates selftesting and self-repairing structures in the memory. As a result, the memory chips can perform tests, locate faults, and repair itself without any external assistance from either test engineers or test equipment, This will drastically improve the functional yield and reduce the production cost, Secondly… CONTINUE READING

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References

Publications referenced by this paper.
SHOWING 1-9 OF 9 REFERENCES

A 3.3 V 12 ns 16 Mb CMOS RAM,

  • H. Goto
  • 1992

A 10 ns 4 Mb BICMOS ’ITL SRAM,

  • H. Shimada
  • 1991

A 15 ns 16mb CMOS SRAM with reduced

  • M. Matsumiya
  • IEEE Int. Solid-State Circuits Con$,
  • 1991

A 7 ns 4 Mb BICMOS SRAM with a parallel testing

  • Y. Okajima er al
  • IEEE Inr. Solid-State Circuits Con$,
  • 1991

A I /tA retention 4 Mb SRAM with a thin-film '\ transistor load cell,

  • S. Hayakawa el al
  • IEEE Int. Solid-state Circuits Con&,
  • 1990

An 8ns BICMOS lmb ecl SRAM with a configurable memory array size," I989

  • H. Tran
  • IEEE Int. Solid-State Circuits Con&,
  • 1989

Parallel testing technology for vlsi memories,

  • J. Inoue
  • 1987

Design for autonomous test , ” in Proc . IEEE Inr

  • Konemann J. Mucha, G. Zweihoff

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