Design of a novel error detection and correction scheme for pipeline and other multi-stage ADCs with a mono comparator per stage pipeline like architecture

Abstract

The paper describes a novel design that minimizes the effect of small offset errors in comparators of pipeline ADCs. This simple but effective error detection and correction scheme enables to eliminate the requirement of redundant comparators in the stages of a Pipeline ADC. A one bit per stage pipeline like architecture is also proposed. Implementing a… (More)

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