# Design of a Novel Fault Tolerant Reversible Full Adder for Nanotechnology Based Systems

@inproceedings{Haghparast2008DesignOA, title={Design of a Novel Fault Tolerant Reversible Full Adder for Nanotechnology Based Systems}, author={Majid Haghparast and Keivan Navi}, year={2008} }

Reversible computation plays an important role in the synthesis of circuits having application in quantum computing, low power CMOS design, bioinformatics and nanotechnology-based systems. Conventional logic circuits are not reversible. A reversible circuit maps each input vector, into a unique output vector and vice versa. We demonstrate how the well-known and very useful, Toffoli gate can be synthesized from only two parity-preserving reversible gates. Parity preserving reversible gates…

## 88 Citations

### Synthesis of Fault Tolerant Reversible Logic Circuits

- Computer Science2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis
- 2009

It is shown how a fault tolerant reversible full adder circuit can be realized using only two IGs and it has been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.

### Realization of a Novel Fault Tolerant Reversible Full Adder Circuit in Nanotechnology

- Computer Science, EngineeringInt. Arab J. Inf. Technol.
- 2010

This paper presents an efficient realization of well known Toffoli gate using only two parity preserving reversible gates, a novel fault tolerant reversible full adder circuit and its superiority with the existing counterparts.

### Design of a High Performance Reversible Multiplier

- Computer Science, Engineering
- 2011

The proposed 4×4 reversible multiplier circuit has lower hardware complexity and it is much better and optimized in terms of number of reversible gates and number of garbage outputs with compared to the existing counterparts.

### SCOPE OF REVERSIBLE ENGINEERING AT GATE-LEVEL: FAULT-TOLERANT COMBINATIONAL ADDERS

- Computer ScienceVLSIC 2012
- 2012

The proposed reversible gate is designed to have less hardware complexity and efficiecyt in terms of gate count, garbage outputs and constant input, and newly designed TG gates are designed.

### Novel designs of nanometric parity preserving reversible compressor

- Engineering, Computer ScienceQuantum Inf. Process.
- 2014

The proposed parity preserving reversible full adder using NPPG gate is more efficient than the existing designs in term of quantum cost and it is optimized in terms of number of constant inputs and garbage outputs.

### Design and optimization of nanometric reversible 4 bit numerical comparator

- Computer Science2012 International Conference on Informatics, Electronics & Vision (ICIEV)
- 2012

A 4-bit nanometric reversible numerical comparator circuit is proposed, which makes the proposed design more efficient and optimal, and shows that it is much better and optimized in terms of number of garbage outputs with compared to the existing counterparts.

### Design of a Novel Reversible Multiplier Circuit Using HNG Gate in Nanotechnology

- Engineering, Computer Science
- 2008

A novel 4x4 bit reversible multiplier circuit using HNG gate can multiply two 4-bits binary numbers and can be generalized for NxN bit multiplication.

### Designing a Novel Nanometric Parity Preserving Reversible ALU

- Computer Science
- 2013

A novel nanometric reversible ALU is proposed which uses parity preserving reversible gates as its basic building blocks and is optimized in terms of quantum cost, the number of garbage outputs, thenumber of constant inputs and hardware complexity.

### Design of fast fault tolerant reversible signed multiplier

- Computer Science, Engineering
- 2012

Simulation and evaluation results indicate that the multiplier logic structure is correct with excellent performance, and it can work independently as a reversible fault tolerant full adder.

### Novel Synthesis Methodology for Fault Tolerant Reversible Circuits by Bounded Model Checking for Linear Temporal Logic

- Computer ScienceJ. Circuits Syst. Comput.
- 2015

The formal method to synthesis small fault tolerant gate, so as to construct the circuit with robust (semi) parity-preserving gates, which is conducive to detecting the stuck-at fault and partial gate fault in reversible circuits.

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