Corpus ID: 212598528

Design of a High-Speed, Low-Power, Area- Efficient 8-bit Vedic Multiplier Using Urdhva- Tiryagbhyam Theorem & Modified GDI Cells

@inproceedings{Tiwari2017DesignOA,
  title={Design of a High-Speed, Low-Power, Area- Efficient 8-bit Vedic Multiplier Using Urdhva- Tiryagbhyam Theorem & Modified GDI Cells},
  author={Ravi Tiwari and Bobby Nelson},
  year={2017}
}
  • Ravi Tiwari, Bobby Nelson
  • Published 2017
  • The paper presents the implementation of a low-power and area-efficient 8-bit multiplier using the concepts of ancient Vedic Mathematics, more specifically the Urdhva-Tiryagbhyam (UT) theorem. We aim to design the aforementioned multiplier using Modified-Gate-Diffusion-Input cells (Mod-GDI), which facilitate the reduction of transistor count while maintaining a full voltage swing, thereby, consuming even lower power than the CMOS implementation of the Vedic Multiplier. The multipliers are one… CONTINUE READING

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