Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits

@article{Calimera2009DesignOA,
  title={Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits},
  author={Andrea Calimera and Luca Benini and Alberto Macii and Enrico Macii and Massimo Poncino},
  journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
  year={2009},
  volume={56},
  pages={1979-1993}
}
Power-gating is one of the most promising and widely adopted solutions for controlling sub-threshold leakage power in nanometer circuits. Although single-cycle power-mode transition reduces wake-up latency, it develops large discharge current spikes, thereby causing IR-drop and inductive ground bounce for the neighboring circuit blocks, which can suffer from power plane integrity degradation. We propose a new reactivation solution that helps in controlling power supply fluctuations and… CONTINUE READING
Highly Cited
This paper has 28 citations. REVIEW CITATIONS

Citations

Publications citing this paper.
Showing 1-10 of 18 extracted citations

Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) • 2010
View 13 Excerpts
Highly Influenced

A New Memory Banking System for Energy-Efficient Wireless Sensor Networks

2013 IEEE International Conference on Distributed Computing in Sensor Systems • 2013
View 1 Excerpt

A low-voltage, Low-Power 4-bit BCD adder, designed using the Clock Gated Power Gating, and the DVT scheme

2013 IEEE International Conference on Signal Processing, Computing and Control (ISPCC) • 2013
View 2 Excerpts

Enhanced reduction of ground bounce noise in low leakage CMOS multiplier with combinational MTCMOS circuit

2013 IEEE International Conference on Signal Processing, Computing and Control (ISPCC) • 2013
View 1 Excerpt

References

Publications referenced by this paper.
Showing 1-10 of 29 references

Body Bias Voltage Computations for Process and Temperature Compensation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems • 2008
View 1 Excerpt

Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting

2008 Design, Automation and Test in Europe • 2008
View 1 Excerpt

A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems • 2007
View 1 Excerpt

Similar Papers

Loading similar papers…