Design of a Fastbus Programmable Sequencer Module

Abstract

A programmable sequencer and a memory module have been designed and built to demonstrate high speed operation of the FASTBUS, and to study design implications of the FASTBUS specification. Both are implemented in ECL, and illustrate master and slave operation, arbitration circuit design, and logical and geographical addressing considerations.

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Cite this paper

@inproceedings{Bertolucci1999DesignOA, title={Design of a Fastbus Programmable Sequencer Module}, author={B . Bertolucci and D. Horelick}, year={1999} }