Design of a Bit-Serial Floating Point Unit for a Fine Grained Parallel Processor Array

Abstract

This paper presents the design of a new bit-serial floating-point unit (FPU). It has been developed for the processors of the Instruction Systolic Array parallel computer model. In contrast to conventional bit-parallel FPUs the bit-serial approach requires different data formats. Our FPU uses an IEEE compliant internal floating point format that allows a fast least significant bit (LSB)-first arithmetic and can be efficiently implemented in hardware.

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Cite this paper

@inproceedings{Schimmler2003DesignOA, title={Design of a Bit-Serial Floating Point Unit for a Fine Grained Parallel Processor Array}, author={Manfred Schimmler and Bertil Schmidt and Hans-Werner Lang}, booktitle={PDPTA}, year={2003} }