Design of a 90nm 4-CPU 4320MIPS SoC with individually managed frequency and 2.4GB/s multi-master on-chip interconnect

@article{Nishii2007DesignOA,
  title={Design of a 90nm 4-CPU 4320MIPS SoC with individually managed frequency and 2.4GB/s multi-master on-chip interconnect},
  author={Osamu Nishii and Itaru Nonomura and Yutaka Yoshida and Kiyoshi Hayase and Shinichi Shibahara and Yoshitaka Tsujimoto and Masashi Takada and Tetsuya Hattori},
  journal={2007 IEEE Asian Solid-State Circuits Conference},
  year={2007},
  pages={18-21}
}
We have developed a 97.6 mm2 SoC that includes four SuperHtrade architecture CPUs and a DDR-2 controller with 90-nm CMOS for high-performance embedded applications. These four 600 MHz CPUs are identical and each has a floating point unit, 32/32 KB cache memory, and 152 KB local memory. CPUs totally achieve performance of 4320MIPS. Main on-chip 300 MHz 64-bit bus manages processors access and another dedicated connection holds cache coherency operation. Considering varying processing load, this… CONTINUE READING
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