Design of a 4-bit 1.4 Gsamples/s low power folding ADC for DS-CDMA UWB transceivers


In this paper, we present a CMOS low power folding ADC (analog to digital converter) architecture, which takes advantage of the low resolution requirement of DS-CDMA UWB transceivers to reduce the power consumption. The high sampling rate is achieved by adopting current steering folding amplifiers instead of cross coupled differential pair based folding… (More)


13 Figures and Tables

Slides referencing similar topics