Design of a 2.5Gbps Clock-Data Recovery circuit in 0.18um standard CMOS process

@article{Yueyang2009DesignOA,
  title={Design of a 2.5Gbps Clock-Data Recovery circuit in 0.18um standard CMOS process},
  author={Chen Yueyang and Zhong Shun'an and Dang Hua},
  journal={2009 IEEE 8th International Conference on ASIC},
  year={2009},
  pages={1153-1156}
}
A 2.5Gbps Clock-Data Recovery (CDR) circuit is designed in 0.18um standard CMOS process in this work. The CDR circuit utilizes one PLL loop and one CMU loop. The CDR loop works at 2.5GHz by SONET OC-48 while the CMU loop runs at 625MHz.The power consumption is 25mW. The jitter bandwidth is 5.6MHz. The peaking is 2.67dB. The VCO gain is 163MHz/V with a… CONTINUE READING