Design of a 2-GS/s 8-b self-calibrating ADC in 0.18 /spl mu/m CMOS technology

@article{Azzolini2005DesignOA,
  title={Design of a 2-GS/s 8-b self-calibrating ADC in 0.18 /spl mu/m CMOS technology},
  author={Cristiano Azzolini and Andrea Boni and Alessio Facen and Matteo Parenti and Davide Vecchi},
  journal={2005 IEEE International Symposium on Circuits and Systems},
  year={2005},
  pages={1386-1389 Vol. 2}
}
The paper discusses the design of a very highspeed 8-b analog-to-digital converter (ADC) in 0.18-/spl mu/m CMOS. A conversion rate as high as 2GS/s with a relatively low power consumption was achieved by means of a couple of interleaved subranging/flash ADC with a single track-and-hold at the input. Special design solutions were adopted for implementing subranging operation at such a high frequency. Finally, a lower power consumption self-calibrating technique effective for reducing… CONTINUE READING

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