Design of a 100-nanosecond read-cycle NDRO plated-wire memory

@inproceedings{Ishidate1968DesignOA,
  title={Design of a 100-nanosecond read-cycle NDRO plated-wire memory},
  author={T. Ishidate},
  booktitle={AFIPS '68 (Fall, part II)},
  year={1968}
}
  • T. Ishidate
  • Published in AFIPS '68 (Fall, part II) 1968
  • Computer Science
  • Plated-wire memories are now attaining a promising position in main memories. UNIVAC claims that, in the non-destructive readout (NDRO), the cost of peripheral circuit can be reduced, since peripheral circuits are useful enough to maintain multiple words. However, the NDRO is most effective only for slower memories with a comparatively small number of interface bits. The main memories such as 72-bit-per-word 100-nsec read-cycle memory system cannot be improved by the use of the NDRO as… CONTINUE READING
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