Design of a 1.8V 8-bit 500MSPS folding-interpolation CMOS A/D converter with a folder averaging technique

@article{Lee2007DesignOA,
  title={Design of a 1.8V 8-bit 500MSPS folding-interpolation CMOS A/D converter with a folder averaging technique},
  author={Dongjin Lee and Jaewon Song and Jongha Shin and Sanghoon Hwang and Minkyu Song and Theodore Wysocki},
  journal={2007 18th European Conference on Circuit Theory and Design},
  year={2007},
  pages={356-359}
}
In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 500 MSPS at 1.8 V is designed. The architecture of the proposed ADC is based on a Folding ADC with a cascaded-folding and a cascaded-interpolation structure. A self-linearized preamplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18mu m 1-poly 5-metal CMOS technology… CONTINUE READING
2 Citations
6 References
Similar Papers

Citations

Publications citing this paper.

References

Publications referenced by this paper.
Showing 1-6 of 6 references

An 8-bit Video ADC Incorporation Folding and Interpolation Technique

  • R.Grift. I. Rutten, M. Veen
  • IEEE J. Solid-State Circuits, vol. SC-22, no. 6…
  • 1987
Highly Influential
4 Excerpts

An 8-bit Folding A/D Converter with a New Interpolation Technique

  • Evandro Mazina Martinx, Elnatan Chagas Ferreira
  • Analog Intergrated Circuits and Signal Processing…
  • 2004
2 Excerpts

and Elnatan Chagas Ferreira , “ An 8 - bit Folding A / D Converter with a New Interpolation Technique

  • Evandro Mazina Martinx
  • Analog Intergrated Circuits and Signal Processing
  • 2004

A 12-b 60-MSample/s Cascaded Folding and Interpolation ADC

  • Pieter VorenKamp
  • IEEE J. Solid-State Circuits, vol. 32. 12 1876…
  • 1876
2 Excerpts

Similar Papers

Loading similar papers…