Design of Vedic IEEE 754 floating point multiplier

@article{Havaldar2016DesignOV,
  title={Design of Vedic IEEE 754 floating point multiplier},
  author={Soumya Havaldar and K. Gurumurthy},
  journal={2016 IEEE International Conference on Recent Trends in Electronics, Information \& Communication Technology (RTEICT)},
  year={2016},
  pages={1131-1135}
}
  • Soumya Havaldar, K. Gurumurthy
  • Published 2016
  • Computer Science
  • 2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)
Floating point number can co-occurrently develop a prominent range of numbers and a high level of precision. Multiplication of floating point numbers found extensive use in wider range of technological and commercial calculations. It is needed to implement faster multipliers involving limited area and consuming reduced power. An IEEE-754 format established multiplier applying Vedic Urdhva - Tiryagbhyam mathematics will be cultivated to cover both single precision and double precision format… Expand
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