Design of Sub Threshold Flip Flop For Ultra Low Power Applications

Abstract

Abstract: Power consumption is considered as one of the important challenge in modern VLSI design along with area and speed consideration. Flip flop plays very important role in digital systems. In this paper comparative study of four different flip flops which includes pulse triggered as well as conditional technique flip flop such as IP-DCO, MHLFF, CPSFF, and CPFF topologies in sub threshold operation are examined. In recent years the ultra low power application can be possible using sub threshold technology. Using the advantage of this technology the power consumption of these flip flops is minimized. Sub threshold circuit consume less power than strong inversion circuit at the same frequency. Design is done using HSPICE in TSMC 180nm technology. The flip flops are analysed in all corners and parameters such as delay, power delay product, Energy delay product, and average power is measured at power supply voltage 300mV, and applied clock frequency is 1 MHz at temperature of 27C

2 Figures and Tables

Cite this paper

@inproceedings{Harish2014DesignOS, title={Design of Sub Threshold Flip Flop For Ultra Low Power Applications}, author={Madge Deepali Harish and Abdul Kadir Kureshi}, year={2014} }