• Corpus ID: 5861994

Design of Process Variation 3T1D-Based DRAM Using CADENCE

  title={Design of Process Variation 3T1D-Based DRAM Using CADENCE},
  author={A. Yadav and P. Tete},
ady.29arpit@gmail.com aruna.mathurkar@gmail.com Abstract— This Paper Deals With the Design and Analysis of 3T1D DRAM Cell to develop Process Variation Architectures using Cadence Tool. With continued technology scaling, process variations will be especially Detrimental to Threetransistor One Diode Dynamic memory structures (3T1D DRAM). A Memory architecture using three-transistor, onediode DRAM (3T1D) cells Using Cadence tool wide process variations with Different Technology 0.6um ami, 0.40um… 


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  • 2009
FinFET variants of the bulk gated-diode configuration and parameters that are critical to enhancing the retention time and read current in 2T/3T1D FinFET DRAMs are proposed and identified.
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  • J. Poulton
  • Engineering, Computer Science
    Proceedings Seventeenth Conference on Advanced Research in VLSI
  • 1997
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