Design of New Low Power – Area Efficient Static Flip-Flops

@inproceedings{Kumar2014DesignON,
  title={Design of New Low Power – Area Efficient Static Flip-Flops},
  author={M. Jagadeesh Kumar and Dr. R. Ramana Reddy},
  year={2014}
}
System on chip (SOC) design integrates many complex modules in one chip. As number of modules per chip is increasing, number of transistors in a chip increases resulting in increase in area and power dissipation. Area and power dissipation problems can be most effectively addressed if the basic building blocks of the circuit are designed for lower power… CONTINUE READING