Design of Low Power Risc Processor by Applying Clock Gating Technique

  title={Design of Low Power Risc Processor by Applying Clock Gating Technique},
  author={J. V. R. Ravindra and T. Anuradha},
  journal={International Journal of Computer Applications},
Power has become a primary consideration during hardware design. Dynamic power can contribute up to 50% of the total power dissipation. Clock-gating is the most common RTL optimization for reducing dynamic power. By applying Effective clock-gating technique on RISC processor adds additional logic to the existing synchronous circuit to prune the clock tree, thus disabling the portions of the circuitry that are not in use. Here in this project designed and developed efficient RISC CPU Interrupt… Expand
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