Design of Low Power 4-bit ALU Using Adiabatic Logic

@article{Turaga2014DesignOL,
  title={Design of Low Power 4-bit ALU Using Adiabatic Logic},
  author={Sriraj Dheeraj Turaga and Kundan Vanama and Rithwik Reddy Gunnuthula and K. Jaya Datta Sai},
  journal={IOSR journal of VLSI and Signal Processing},
  year={2014},
  volume={4},
  pages={43-48}
}
This paper presents the implementation of a 4-bit Arithmetic Logic Unit (ALU) using Complementary Energy Path Adiabatic Logic (CEPAL. [...] Key Method Firstly, the performance characteristics of CEPAL 4-to-1 multiplexer and full adder are compared against the conventional static CMOS logic counterpart to identify its adiabatic power advantage. Finally, A 4-bit Arithmetic Logic Unit (ALU) is implemented with both the technologies and comparisons have been made.Expand
1 Citations
Investigation of Homo and Hetero-Junction Double-Gate Tunnel-FET-Based Adiabatic Inverter Circuits
This paper compares the performance of adiabatic inverter circuits employing homo/hetero-junction-based double-gate tunnel field-effect transistors (DG-TFETs). The static and dynamic adiabatic inve...

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