Design of Low Power 4-bit ALU Using Adiabatic Logic

  title={Design of Low Power 4-bit ALU Using Adiabatic Logic},
  author={Sriraj Dheeraj Turaga and Kundan Vanama and Rithwik Reddy Gunnuthula and Kohan Sai},
  journal={IOSR journal of VLSI and Signal Processing},
This paper presents the implementation of a 4-bit Arithmetic Logic Unit (ALU) using Complementary Energy Path Adiabatic Logic (CEPAL. [...] Key Method Firstly, the performance characteristics of CEPAL 4-to-1 multiplexer and full adder are compared against the conventional static CMOS logic counterpart to identify its adiabatic power advantage. Finally, A 4-bit Arithmetic Logic Unit (ALU) is implemented with both the technologies and comparisons have been made.Expand
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This paper compares the performance of adiabatic inverter circuits employing homo/hetero-junction-based double-gate tunnel field-effect transistors (DG-TFETs). The static and dynamic adiabatic inve...


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The main and highly concerned issue in the low power VLSI design circuits is Power dissipation. The basic approaches that we used for reducing energy/power dissipation in conventional CMOS circuits
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Low power has emerged as a principle theme in today electronic industry. Energy efficiency is one of the most important features of modern electronic systems designed for high speed and portable
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In this paper, a new design of adiabatic circuit, called energy efficient adiabatic logic (EEAL) is proposed. Earlier various diode based adiabatic logic families have been proposed. To achieve
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In this paper, low power multiplier design using complementary pass-transistor asynchronous adiabatic logic is investigated. Adiabatic circuits are very low power circuits compared with CMOS logic