Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding

@article{Ganguly2008DesignOL,
  title={Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding},
  author={Amlan Ganguly and Partha Pratim Pande and Benjamin Belzer and Cristian Grecu},
  journal={J. Electronic Testing},
  year={2008},
  volume={24},
  pages={67-81}
}
Network on Chip (NoC) is an enabling methodology of integrating a very high number of intellectual property (IP) blocks in a single System on Chip (SoC). A major challenge that NoC design is expected to face is the intrinsic unreliability of the interconnect infrastructure under technology limitations. Research must address the combination of new device-level defects or error-prone technologies within systems that must deliver high levels of reliability and dependability while satisfying other… CONTINUE READING
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A (2005) New ECC for Crosstalk Effect Minimization

  • D Rossi, C Metra, AK Nieuwland, Katoch
  • IEEE Des Test Comput
  • 2005
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