• Corpus ID: 14573557

Design of Low Power & High Speed Comparator with 0.18µm Technology for ADC Application

  title={Design of Low Power \& High Speed Comparator with 0.18µm Technology for ADC Application},
  author={Rohit Mongre and R. C. Gurjar},
In Analog to Digital Converter (ADC), high speed comparator influences the overall performance of ADC directly. This paper presents the high speed & low power design of a CMOS comparator. Schematic design of this comparator is fabricated in a 0.18µm UMC Technology with 1.8V power supply and simulated in cadence Virtuoso. Simulation results are presented and it shows that this design can work under high speed of 0.8108 GHz. The design has a low offset voltage, low power dissipation 108.0318µw… 

Figures and Tables from this paper

A 10GHZ Low-Offset Dynamic Comparator for High-Speed and Lower-Power ADCS

This paper proposed a design of low-voltage Dynamic Comparator using 90 nm PTM CMOS technology for high-speed and Lower-power Analog to Digital Converter (ADC) applications and shows 5.7 mV offset, small when compared to other dynamic comparators and preamplifier based comparators.

Review on Comparator Design for High Speed ADCs

The survey on CMOS comparators shows the specifications of different topologies and further advancement in comparator is necessary as downscaling of technology is increasing.

Simulative Analysis of Low-Power CMOS Comparators for Wireless Communication

This paper presents two topologies of low power CMOS comparators that are simulated in Mentor Graphics software using TSMC.18μm technology. The circuits studied and simulated in this paper are



Design and Analysis of Low Power and High Speed Dynamic Latch Comparator in 0 . 18 μ m CMOS Process

The designed dynamic latch comparator is required for high-speed analog-to-digital converters to get faster signal conversion and to reduce the power dissipation, which is immune to noise than the previous works.

Design of Low Power and High Speed CMOS Comparator for A/D Converter Application

An improved method for design of CMOS comparator based on a preamplifier-latch circuit driven by a clock capable to reduce power dissipation and increase speed of an ADC is presented.

High speed with low power folding and interpolating ADC using two types of comparator in CMOS 0.18um technology

The simulation results indicate that the comparator design 1 achieved lower power operation rather than comparators design 2 with a minimum number of transistors used, 2GHz of input signal and 497.02mW of power consumption from a single 2V supply based to Gateway Silvaco EDA tools simulation result.

Design techniques for high-speed, high-resolution comparators

Precision techniques for the design of comparators used in high-performance analog-to-digital converters employing parallel conversion stages are described. Following a review of conventional offset

A CMOS low-power low-offset and high-speed fully dynamic latched comparator

A novel dynamic latched comparator is presented that demonstrates lower offset voltage and higher load drivability than the conventional double-tail dynamic comparators.

On the design of low-power CMOS comparators with programmable hysteresis

We compare designs of low-power CMOS comparators with programmable hysteresis. We chose two baseline comparators: a two-stage CMOS op-amp with output inverter and a folded-cascode op-amp with output

Design and Implementation a 8 bits Pipeline Analog to Digital Converter in the Technology 0.6µm CMOS Process

This paper describes a 8 bits, 20 Msamples/s pipeline analog-to-digital converter implemented in 0.6 \mu m CMOS technology with a total power dissipation of 75.47 mW. Circuit techniques used include

ROBERTS ' and Molianiad SA WAN “ A 1V , 1 0bit RailtoRail Successive Approximation AnalogtoDigital Converter in Standard 0