Corpus ID: 14573557

Design of Low Power & High Speed Comparator with 0.18µm Technology for ADC Application

@inproceedings{Mongre2014DesignOL,
  title={Design of Low Power & High Speed Comparator with 0.18µm Technology for ADC Application},
  author={Rohit Mongre and R. Gurjar},
  year={2014}
}
  • Rohit Mongre, R. Gurjar
  • Published 2014
  • Engineering
  • In Analog to Digital Converter (ADC), high speed comparator influences the overall performance of ADC directly. This paper presents the high speed & low power design of a CMOS comparator. Schematic design of this comparator is fabricated in a 0.18µm UMC Technology with 1.8V power supply and simulated in cadence Virtuoso. Simulation results are presented and it shows that this design can work under high speed of 0.8108 GHz. The design has a low offset voltage, low power dissipation 108.0318µw… CONTINUE READING
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    References

    SHOWING 1-10 OF 16 REFERENCES
    Design of Low Power and High Speed CMOS Comparator for A/D Converter Application
    • 21
    • PDF
    High speed with low power folding and interpolating ADC using two types of comparator in CMOS 0.18um technology
    • 6
    A CMOS low-power low-offset and high-speed fully dynamic latched comparator
    • 66
    • PDF
    On the design of low-power CMOS comparators with programmable hysteresis
    • 25
    • PDF
    CMOS Analog Circuit Design
    • 2,619
    • PDF
    Rahman“Design and Analysis of Low Power and High Speed Dynamic Latch Comparator in 0.18 μm CMOS Process
    • International Journal of Information and Electronics Engineering,
    • 2012
    A 1- V, 1 0-bit Rail-to-Rail Successive Approximation Analog-to-Digital Converter in Standard 0.18pm CMOS Technology
    • A 1- V, 1 0-bit Rail-to-Rail Successive Approximation Analog-to-Digital Converter in Standard 0.18pm CMOS Technology