Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM)

@article{Xu2011DesignOL,
  title={Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM)},
  author={Wei Xu and Hongbin Sun and Xiaobin Wang and Yiran Chen and Tong Zhang},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2011},
  volume={19},
  pages={483-493}
}
Because of its high storage density with superior scalability, low integration cost and reasonably high access speed, spin-torque transfer random access memory (STT RAM) appears to have a promising potential to replace SRAM as last-level on-chip cache (e.g., L2 or L3 cache) for microprocessors. Due to unique operational characteristics of its storage device magnetic tunneling junction (MTJ), STT RAM is inherently subject to a write latency versus read latency tradeoff that is determined by the… CONTINUE READING
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