Design of High-speed CMOS Frequency Dividers for RF Receiver

@article{Tang2007DesignOH,
  title={Design of High-speed CMOS Frequency Dividers for RF Receiver},
  author={Lu Tang and Zhigong Wang and Xiao-Hu He and Zhi-qun Li and Yong Xu},
  journal={2007 International Conference on Microwave and Millimeter Wave Technology},
  year={2007},
  pages={1-4}
}
A divide-by-16/17 dual-modulus prescaler (DMP) and two programmable & plus swallow dividers for application in a digital video broadcasting-terrestrial (DVB-T) receiver are designed in a 0.18mum 3.3V mixed-signal CMOS process. The master/slave D-flip-flop (DFF) in the DMP is made up of an improved D-latch to increase the speed and the driving capability. A novel D-latch architecture integrated with 'OR' logic is proposed to decrease the complexity of the circuit. Post simulation results of the… CONTINUE READING

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