• Corpus ID: 212467566

Design of High Speed Comparator

@inproceedings{Karwarker2014DesignOH,
  title={Design of High Speed Comparator},
  author={Jayesh Shetti Karwarker},
  year={2014}
}
A new CMOS dynamic comparator using dual input single output differential amplifier as latch stage suitable for high speed analog-to-digital converters with High Speed, low power dissipation and immune to. Back-to-back inverter in the latch stage is replaced with dual-input single output differential amplifier. This topology completely removes the noise that is present in the input. The structure shows lower power dissipation and higher speed than the conventional comparators. The circuit is… 

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