Design of Gating Pulse Generation on FPGA using CORDIC Algorithm for Cascaded Multi- Level Inverter

@inproceedings{Kumar2013DesignOG,
  title={Design of Gating Pulse Generation on FPGA using CORDIC Algorithm for Cascaded Multi- Level Inverter},
  author={Vinay Kumar and Sanjay Lakshminarayanan},
  year={2013}
}
In this paper, FPGA based gate triggering pulses for five-level Cascaded Multilevel Inverter is designed. CORDIC algorithm is implemented on FPGA which is used for calculating different sine values. These sine values are used for generating gate pulses of five-level cascaded multilevel inverter. MATLAB/SIMULINK software was used for simulation and verification of proposed method.Gating signals are generated using FPGA Spartan-2 processor. The processor is designed using Verilog HDL using a… CONTINUE READING