Design of Efficient Reversible Multiply Accumulate (MAC) Unit

  title={Design of Efficient Reversible Multiply Accumulate (MAC) Unit},
  author={Christopher H. Bennett and Palanirajan Vijayaraj Kumar and Sastry Hari and Shyam Shroff and Sk Noor Mahammad and V. Kamakoti and Nagarajan Ranga Ranganathan and Min-Lun Chuang and Chun-Yao Wang and Mohammad Samadi Gharajeh},
The multiplication and accumulation are the vital operations involved in almost all the Digital Signal Processing applications. Consequently, there is a demand for high speed processors having dedicated hardware to enhance the speed with which these multiplications and accumulations are performed. In the present conventional circuits, the multiply accumulate unit multiplies the two operands, adds the product to the previously accumulated result and stores back the new result in the accumulator… CONTINUE READING