Corpus ID: 108359646

Design of Binary Weighted Current Steering DAC using OEM Technique

  title={Design of Binary Weighted Current Steering DAC using OEM Technique},
  author={P. Karthika and T. Madhubala and T. Chelladurai},
  journal={International journal of engineering research and technology},
This paper describes reduction of mismatch in binary weighted current steering DAC. The mismatch is a major problem occurred in DAC, whenever signal is converted from digital to analog. Due to this resolution and accuracy of the DAC get affected. To avoid this problem ordered element matching (OEM) technique is proposed. OEM technique used to order the elements to avoid mismatch in order to improve the performance of the DAC. The method was done by 15bit binary weighted current steering DAC… Expand

Figures and Tables from this paper


A random DEM technique with minimal element transition rate for high-speed DACs
  • Peijun Wang, Nan Sun
  • Computer Science
  • 2014 IEEE International Symposium on Circuits and Systems (ISCAS)
  • 2014
A random dynamic element matching (DEM) technique for current-steering digital-to-analog converters (DACs) that randomizes the element selection process, and keeps the number of transitions to minimum. Expand
A CMOS 8-bit binary type current steering Digital to Analog Converter DAC with dynamic random return to zero technique to improve dynamic performance is presented in this paper. Current steering DACExpand
Models and Implementation of a Dynamic Element Matching DAC
A model describing the dynamic properties of a DEM DAC is presented and the simulated results with measurements of a 14-bit current-steering DEM DAC implemented in a 0.35-μm CMOS process show that the measured data agrees well with the results predicted by the used model. Expand
A low-glitch binary-weighted DAC with delay compensation scheme
This paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted current-steering digital-to-analog converter (DAC). Instead of using large input buffers to drive a lotExpand
The analysis and improvement of a current-steering DACs dynamic SFDR-I: the cell-dependent delay differences
  • Tao Chen, G. Gielen
  • Engineering, Computer Science
  • IEEE Transactions on Circuits and Systems I: Regular Papers
  • 2006
The delay differences cancellation (DDC) technique to reduce the impact of the delay differences on the SFDR property is proposed and verified by simulation results. Expand
Random Swapping Dynamic Element Matching Technique for Glitch Energy Minimization in Current-Steering DAC
A type of the DEM method called random swapping thermometer coding for the implementation of Nyquist-rate current-steering digital-to-analog converters is described, which can minimize the number of switched elements as codes change, while achieving good spectrum purity as other DEM implementations. Expand
A 10-bit 250-MS/s binary-weighted current-steering DAC
The obtained 60 dB SFDR in this measurement demonstrates that the binary nature of the converter did not limit the SFDR, and a method for reducing the segmentation degree is given. Expand
A 12-Bit 1-Gsample/s Nyquist Current-Steering DAC in 0.35 µm CMOS for Wireless Transmitter
The present work deals with 12-bit Nyquist current-steering CMOS digital-to-analog converter (DAC) which is an essential part in baseband section of wireless transmitter circuits. Using oversamplingExpand
A CMOS 8-Bit 1.6-GS/s DAC With Digital Random Return-to-Zero
A digital random return-to-zero technique is presented to improve the dynamic performance of current-steering digital- to-analog converters (DACs) and achieves a spurious-free dynamic range better than 60 dB for a sine-wave input up to 460 MHz. Expand
An Order-Statistics Based Matching Strategy for Circuit Components in Data Converters
  • Tao Zeng, Degang Chen
  • Mathematics, Computer Science
  • IEEE Transactions on Circuits and Systems I: Regular Papers
  • 2013
This paper introduces a novel random mismatch compensation theory called ordered element matching, which effectively reduces the standard deviation of the mismatch errors by a factor of at least 6.5 in a reasonably sized component population. Expand