Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicrometer CMOS Circuits

Abstract

As the devices are scaling down, the combinational logic will become susceptible to soft errors. The conventional soft error tolerant methods for soft errors on combinational logic do not provide enough high soft error tolerant capability with reasonably small performance penalty. This paper investigates the feasibility of designing quasi-delay insensitive… (More)
DOI: 10.1109/TVLSI.2008.2011554

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Cite this paper

@article{Kuang2010DesignOA, title={Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicrometer CMOS Circuits}, author={Weidong Kuang and Peiyi Zhao and Jiann S. Yuan and Ronald F. DeMara}, journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, year={2010}, volume={18}, pages={410-422} }