Design of 16-bit Vedic Multiplier for Convolutional Encoder using VHDL

@inproceedings{Dagamwar2017DesignO1,
  title={Design of 16-bit Vedic Multiplier for Convolutional Encoder using VHDL},
  author={Bhagyashree V. Dagamwar and Student Mtech and R. N. Mandavgane and D. M. Khatri},
  year={2017}
}
  • Bhagyashree V. Dagamwar, Student Mtech, +1 author D. M. Khatri
  • Published 2017
In general, multiplication plays an vital role in the development of processors, DSP applications, image processing etc. So, designing of high speed multiplier is a neccesary choice. In this research, design of 4, 8 and 16-bit multiplier based on vedic mathematics has been presented. These multipliers further will be used in the design of convolutional encoder. Here, Urdhava Tiryakbhyam sutra is used for multiplication. It eliminates unwanted multiplication steps and