Design of 16-bit Vedic Multiplier for Convolutional Encoder using VHDL

  • Bhagyashree. V. Dagamwar, R. N. Mandavgane, +8 authors V. Charishma
  • Published 2017

Abstract

In general, multiplication plays an vital role in the development of processors, DSP applications, image processing etc. So, designing of high speed multiplier is a neccesary choice. In this research, design of 4, 8 and 16-bit multiplier based on vedic mathematics has been presented. These multipliers further will be used in the design of convolutional… (More)

Topics

Figures and Tables

Sorry, we couldn't extract any figures or tables for this paper.