Design of 16-bit Multiplier Using Efficient Recoding Techniques

@article{Swamy2015DesignO1,
  title={Design of 16-bit Multiplier Using Efficient Recoding Techniques},
  author={K. N. Narendra Swamy and Jami Venkata Suman},
  journal={International Journal of Hybrid Information Technology},
  year={2015},
  volume={8},
  pages={7-14}
}
  • K. Swamy, J. V. Suman
  • Published 31 October 2015
  • Computer Science
  • International Journal of Hybrid Information Technology
Multiplier is the major component for processing of large amount of data in DSP applications. Using different recoding schemes in Fused Add-Multiply (FAM) design for the reduction of power and look up tables. The performance of 16-bit signed and unsigned multipliers were designed and obtained results are tabulated using Efficient Modified Booth Recoding (EMBR) techniques, which can be used for low power applications. 

Figures and Tables from this paper

References

SHOWING 1-10 OF 10 REFERENCES

Implementation of Modified Booth Algorithm ( Radix 4 ) and its Comparison with Booth Algorithm ( Radix-2 )

TLDR
This paper describes implementation of radix-4 Modified Booth Multiplier and this implementation is compared with Radix-2 BoothMultiplier, a new architecture of multiplier and accumulator for high speed arithmetic by combining multiplication with accumulation and devising a carry-lookahead adder (CLA).

Booth Multiplier: Ease of multiplication

Multiplication in hardware can be implemented in two ways either by using more hardware for achieving fast execution or by using less hardware and end up with slow execution. The area and speed of

Design Issues and Implementations for Floating-Point Divide–Add Fused

TLDR
This brief presents a dedicated unit for the combined operation of floating-point (FP) division followed by addition/subtraction-the divide-add fused (DAF), and presents the impact of the adopted number of quotient bits on accuracy, cost, and performance.

A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology

A 54 b*54 b multiplier fabricated in a double-metal 0.5 mu m CMOS technology is described. The 54 b*54 b full array is adopted to complete multiplication within one latency. A 10 ns multiplication

Area, Delay And Power Comparison Of Adder Topologies

TLDR
The pertinent choice for selecting the adder topology with the tradeoff between delay, power consumption and area is presented and ripple carry adder is presented.

A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit

TLDR
This work proposes a high-speed and energy-efficient two-cycle multiply-accumulate (MAC) architecture that supports two's complement numbers, and includes accumulation guard bits and saturation circuitry, and extends the new architecture to create a versatile double-throughput MAC (DTMAC) unit that efficiently performs either multiply- Accumulate or multiply operations for N-bit, 1 × N/2- bit, or 2 × N-2-bit operands.

Optimized synthesis of sum-of-products

  • R. ZimmermannD. Tran
  • Computer Science
    The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003
  • 2003
In our latest approach to datapath synthesis from RTL, datapaths are extracted into largest possible sum-of-product (SOP) blocks, thus making extensive use of carry-save intermediate results and

Design of Efficient and Fast Multiplier Using MB Recoding Techniques

    A high-performance and low-power 32-bit multiply-accumulate unit with single-instruction-multiple-data (SIMD) feature

    TLDR
    A high-performance and low-power 32-bit multiply-accumulate unit (MAC) is described in this paper, which leverages the advantage of a 16-bit encoding scheme without adding extra delay to the faster four-stage Wallace tree of a 12- bit encoding scheme.

    An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator

    TLDR
    This work introduces a structured and efficient recoding technique and explores three different schemes by incorporating them in FAM designs to implement the direct recoding of the sum of two numbers in its Modified Booth (MB) form.