Design of 16-bit Multiplier Using Efficient Recoding Techniques

  title={Design of 16-bit Multiplier Using Efficient Recoding Techniques},
  author={K. N. Narendra Swamy and Jami Venkata Suman},
  journal={International Journal of Hybrid Information Technology},
  • K. Swamy, J. V. Suman
  • Published 31 October 2015
  • Computer Science
  • International Journal of Hybrid Information Technology
Multiplier is the major component for processing of large amount of data in DSP applications. Using different recoding schemes in Fused Add-Multiply (FAM) design for the reduction of power and look up tables. The performance of 16-bit signed and unsigned multipliers were designed and obtained results are tabulated using Efficient Modified Booth Recoding (EMBR) techniques, which can be used for low power applications. 

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