Design in the Power-Limited Scaling Regime

  title={Design in the Power-Limited Scaling Regime},
  author={Borivoje Nikolic},
  journal={IEEE Transactions on Electron Devices},
Technology scaling has entered a new era, where chip performance is constrained by power dissipation. Power limits vary with the application domain; however, they dictate the choices of technology and architecture and necessitate implementation techniques that tradeoff performance for power savings. This paper examines technology options in the power-limited-scaling regime and reviews sensitivity-based analysis that can be used for the optimal selection of optimal architectures and circuit… CONTINUE READING
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