Design-for-testability techniques for detecting delay faults in CMOS/BiCMOS logic families

  title={Design-for-testability techniques for detecting delay faults in CMOS/BiCMOS logic families},
  author={Koomran Raahemifar and Majid Ahmadi},
  journal={IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing},
  • K. Raahemifar, M. Ahmadi
  • Published 1 November 2000
  • Computer Science
  • IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing
The delay fault testing in logic circuits is studied. It is shown that by detecting delayed time response in a transistor circuit, two types of faults are detected: (1) faults which cause delayed transitions at the output node due to some open defects and (2) faults which cause an intermediate voltage level at the output node. A test circuit is presented which enables the concurrent detection of delay faults. The proposed delay fault testing circuit does not substantially degrade the speed of… 
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