Design for reliability for low power digital circuits

  • Sriram Kalpat
  • Published 2014 in
    Proceedings of Technical Program - 2014…

Abstract

Summary form only given. Lower power digital circuits in cellular phones, laptop or tablet computers have critical power consumption limitations. Power consumption at process corners can vary as much as 50%. In order to optimize high-speed logic circuit designs for low power needs, we need to accurately predict device to product aging across process… (More)
DOI: 10.1109/VLSI-DAT.2014.6834932

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Cite this paper

@article{Kalpat2014DesignFR, title={Design for reliability for low power digital circuits}, author={Sriram Kalpat}, journal={Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test}, year={2014}, pages={1-1} }