Design for improved NBTI reliability of CMOS digital IC

@article{Lining2010DesignFI,
  title={Design for improved NBTI reliability of CMOS digital IC},
  author={Liu Lining and Li Bin and Zhao Mingjian and Xie Yuan Jiang},
  journal={2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC)},
  year={2010},
  pages={1-4}
}
A methodology to mitigate the degradation of digital circuits due to negative bias temperature instability (NBTI) at the view of circuit topology has been put forward in this work. With this approach, simple and strengthened inverter, NAND gate and NOR gate are simulated, the results prove that the proposed strengthened topologies are available to improve NBTI reliability of CMOS digital IC, which is valuable for reliable design against NBTI. 

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