Design for debug: catching design errors in digital chips

  title={Design for debug: catching design errors in digital chips},
  author={Bart Vermeulen and Sandeep Kumar Goel},
  journal={IEEE Design & Test of Computers},
0740-7475/02/$17.00 © 2002 IEEE May–June 2002 MODERN PROCESS TECHNOLOGIES and design tools allow the implementation of very large and complex systems on a single die. With the increased system complexity comes the need for improvements in IC design verification techniques. For multimillion-transistor ICs, existing techniques such as simulation, formal verification, static timing analysis, and emulation cannot guarantee that first silicon will be error free. Examples of design errors that might… CONTINUE READING
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