Design considerations for a 2 MHz synchronous buck converter in CMOS

@article{Fukui2004DesignCF,
  title={Design considerations for a 2 MHz synchronous buck converter in CMOS},
  author={Akimasa Fukui and Jonathan Kipling Knight},
  journal={2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs},
  year={2004},
  pages={71-74}
}
The design considerations for a 2 MHz synchronous buck converter for a cellular phone RF power amplifier supply are presented. Particular emphasis is placed on the problems associated with achieving this high switching frequency with a current-mode architecture and in an inexpensive 0.5 /spl mu/m CMOS process.