Design considerations for 32-bit microprocessor TX3


The architecture of the TX3 implementation of the TRON-CHIP32 specification is discussed. TX3 supports the full instruction set, including the decimal, floating-point, and other complex instructions. Average performance above 10-MIPS is expected. This performance level is obtained by the use of an 8-kB instruction cache, 8-kB data cache, decoded instruction loop buffer, three instruction execution units, and the ability to issue up to two instructions per cycle.<<ETX>>

DOI: 10.1109/CMPCON.1988.4822

Cite this paper

@article{Okamoto1988DesignCF, title={Design considerations for 32-bit microprocessor TX3}, author={Kosei Okamoto and Misao Miyata and Hidechika Kishigami and Takashi Miyamori and T. Sato}, journal={Digest of Papers. COMPCON Spring 88 Thirty-Third IEEE Computer Society International Conference}, year={1988}, pages={25-29} }