Design and verification of a bit error rate tester in Altera FPGA for optical link developments

@inproceedings{Cao2010DesignAV,
  title={Design and verification of a bit error rate tester in Altera FPGA for optical link developments},
  author={Thuong Cao and Jinyi Chang and Datao Gong and Chung-Yen Liu and Tiankuan Liu and An Xiang and Jingbo Ye},
  year={2010}
}
This paper presents a custom bit error rate (BER) tester implementation in an Altera Stratix II GX signal integrity development kit. This BER tester deploys a parallel to serial pseudo random bit sequence (PRBS) generator, a bit and link status error detector and an error logging FIFO. The auto-correlation pattern enables receiver synchronization without specifying protocol at the physical layer. The error logging FIFO records both bit error data and link operation events. The tester’s BER and… CONTINUE READING