Design and validation of a power supply noise reduction technique

  title={Design and validation of a power supply noise reduction technique},
  author={Guoyuan Ji and T. Arabi and G. A. Taylor},
  journal={Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)},
In high performance microprocessors, power supply noise needs to be controlled to ensure reliable high speed bus operation. This is generally done with high quality package capacitors. These capacitors are generally lower equivalent series inductance (ESL) and lower equivalent series resistor (ESR). Contrary to the traditional approach, we will show that a small ESR is not optimal. We will present a novel approach of using an on-die resistor in series with the package capacitance to dampen the… CONTINUE READING
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Beiley, “A Design Methodology for The YO Power Supply of Next Generation Packaging

  • Gang Ji, Tawfik M i, Greg Taylor, Mark
  • Electrical Performance of Electronic Packaging,
  • 2002

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