Design and optimization of SCR devices for on-chip ESD protection in advanced SOI CMOS technologies

Abstract

We present design and optimization results of ESD SCR devices in advanced SOI CMOS technologies. Anode to cathode spacing, body resistance and Diode string or RC trigger circuits affect SCR turn-on characteristics. 100ns TLP failure current up to 10.1mA/um and record transient turn-on time down to ~75ps with a leakage current of ~10nA are demonstrated. 

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