Design and measurement of a small-area 512-Bit EEPROM

Abstract

In this paper, a logic process based small-area 512-bit EEPROM IP for a passive RFID tag chip is designed. We propose a shared CG (Control gate) driver structure in the EEPROM core circuit for a small-area IP design. Devices of 3.3V are limited within 5.5V in the write mode to secure the endurance of 1,000 erase and program cycles as well as ten years of… (More)

Topics

10 Figures and Tables