Design and implementation of line multiplier

Abstract

A multiplier requires an Adder circuitry to add carry of previous result to next stage to form partial products and to get final result of multiplication. This paper presents a novel way to implement Line Multiplier without using Adders. The Adder-less Multiplier is implemented on both CMOS and FPGA platforms. In ASIC paradigm CMOS 90nm technology and on… (More)

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