Design and implementation of hardware architecture for denoising using FPGA


Noise removal in image processing is required in a variety of fields such as object tracking, stereo vision and medical image reconstruction. To obtain accurate results, various video pre-processing is required. We propose a hardware architecture using FPGA to improve the processing speed with the Total Variation algorithm for noise removing images. In the proposed system, we can process images with a resolution of 640 × 480. We remove noise from the input noisy image, after 10 cycles of operations. In the first step, we obtain the right, bottom and center pixel values and the differences to obtain. In the second step, we add pixels to the center of the operation parameters, and the difference between the values are obtained central pixel. The operation parameters and the difference of the values of the surrounding pixels are reflected in the following operations. We repeat this process 10 times to remove the noise in the image. The noise removal performance is better than prior results, but the operation is complex and requires considerable computing power. We implemented the proposed system in hardware that requires high computing power for real-time processing with these processes. The processing delay is 0.8ms. We designed pipeline architecture to delay the operation. The proposed system can operate on image resolution of 640 × 480 with a speed of 250Mhz.

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@article{Jeon2013DesignAI, title={Design and implementation of hardware architecture for denoising using FPGA}, author={ByungMoo Jeon and SangJun Lee and Jungdong Jin and Dung Duc Nguyen and Jae Wook Jeon}, journal={2013 IEEE 9th International Colloquium on Signal Processing and its Applications}, year={2013}, pages={83-88} }